The Intel® Xeon® processor E5-2600 product family reached a new supercomputing milestone as the fastest adopted new processing technology to power 44 systems, including 3 Petascale-class supercomputers on the 39th edition of the Top500 list announced today.
At the International Supercomputing Conference, Intel Corporation also announced that Intel® Xeon® Phi™ is the new brand name for all future Intel® Many Integrated Core Architecture (Intel MIC architecture) based products. Available by the end of 2012, the first generation of Intel Xeon Phi product family (coprocessors codenamed "Knights Corner") will complement the existing Intel Xeon processor E5-2600/4600 product families and deliver new levels of performance for highly parallel workloads. While the first generation primarily targets high performance computing (HPC), future generations of Intel Xeon Phi products will also address enterprise datacenters and workstations.
"The Intel Xeon processor E5 family is powering exponential performance gains in high performance computing and we're proud that it is having such a profound impact on the industry as demonstrated by its presence inside 45 of the Top500 supercomputers," said Raj Hazra, Intel Corporation VP and general manager of the Technical Computing at Data Center and Connected Systems Group. "As we add Intel Xeon Phi products to our portfolio, scientists, engineers and IT professionals will experience breakthrough levels of performance to effectively address challenges ranging from climate change to risk management. This is the next step of Intel's commitment to achieve exascale-level computation by 2018, and create a unique technology category that delivers unprecedented performance for today's highly parallel applications."
First Intel® Xeon® Phi™ Coprocessor Due This Year
Intel disclosed new technical details of the first commercially available product from its Intel Xeon Phi product family, a coprocessor codenamed "Knights Corner." In addition to delivering breakthrough performance for highly parallel applications, Intel Xeon Phi coprocessor's ease of use is bolstered by the benefits of familiar programming models, techniques and developer tools available with Intel architecture. With greater use of parallel CPU code, software companies and IT departments do not have to retrain developers on proprietary programming models associated with accelerators.
Beyond its compatibility with x86 programming models, the Intel Xeon Phi coprocessor will be visible to applications as an HPC-optimized, highly-parallel, separate compute node that runs its own Linux-based operating system independent of the host OS. This feature allows more flexibility when implementing cluster solutions that are not available with alternative graphics accelerator-based technologies.
Made with Intel's innovative 22nm, 3-D tri-gate transistors, the Intel Xeon Phi coprocessor, available in a PCIe form factor, contains more than 50 cores and a minimum of 8GB of GDDR5 memory. It also features 512b wide SIMD support that improves performance by enabling multiple data elements to be processed with a single instruction. Last year Intel showed a live demonstration of the single Knights Corner coprocessor delivering over 1 TeraFLOPs (1 trillion floating point operations per second) of double precision real life performance, as measured by DGEMM. At ISC'12 Intel demonstrated the same effective performance of more than 1 TeraFLOPs per node but measured by the industry standard benchmark Linpack (Rmax)1. By comparison, in 1997, it took more than 9000 Intel® Pentium® processors inside the ASCII RED* supercomputer to break the 1 TeraFLOPs barrier.
While initial production product shipments are planned for the second half of 2012, Intel has announced that the first Intel Xeon Phi coprocessor-based development cluster is up and running and ranked 150th on the Top500 list, delivering 118 TFLOPs of performance.
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